Process for producing a multifunctional dielectric layer on a substrate

ABSTRACT

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

This application is a continuation of co-pending InternationalApplication No. PCT/DE2004/001948, filed Sep. 3, 2004, which designatedthe United States and was not published in English, and which is basedon German Application No. 103 44 389.4, filed Sep. 25, 2003, both ofwhich applications are incorporated herein by reference.

TECHNICAL FIELD

The invention relates to a process for producing a multifunctionaldielectric layer on a substrate, in particular on uncovered metallicinterconnect systems on a substrate.

BACKGROUND

In the semiconductor components that have been disclosed to date, basedon Si substrates, it is predominantly copper interconnects that areresponsible for the electrical contact-connection of the individualfunctional layers or functional elements of a level and also between thelevels. A particular problem that has emerged with the use of copperinterconnects is that Cu atoms can diffuse into the surroundingdielectric and can, therefore, alter the electrical properties of thesemiconductor component, even to the extent of rendering it unable tofunction.

Of course, other substrates, such as glass, GaAs, InP, circuit boards,printed wiring boards, etc., can also be considered as substrates inaddition to Si substrates.

To prevent Cu atoms from diffusing into the dielectric, it is customaryto use diffusion barriers, which are introduced at the side walls of theCu interconnects, i.e., are introduced between the Cu interconnect andthe surrounding dielectric (SiO₂) and consist, for example, of Ta(N).The term Ta(N) used below is in the present context to be understood asmeaning a compound with any desired stoichiometry comprising tantalumand any desired proportion of nitrogen. This ensures sufficientprotection against diffusion.

However, since the copper layer is uncovered at the top following thepatterning of the copper interconnects by means of the standard CMP(chemical mechanical polishing) processing, this copper layer has to bepassivated in order to prevent any oxidation. This is achieved by theuncovered interconnect surface (Cu layer) being provided with a suitabledielectric layer, e.g., SiN-PECVD layer.

However, drawbacks of this interface are the weak point in terms ofelectromigration and stress migration, and the fact that the bonding isless than optimum. By way of example, selective deposition of cobalt onthe uncovered metal surfaces by means of electroless electrolysisprocesses has been attempted with a view to achieving an improvement inthis respect, but this has not to date led to the desired level ofsuccess.

SUMMARY OF THE INVENTION

The invention is now based on the object of providing a process that issimple to implement for the production of a multifunctional passivationlayer for copper interconnects with improved electromigration and stressmigration and improved bonding of the applied dielectric layer.

The object on which the invention is based is achieved, in a process ofthe type described in the introduction, by virtue of the fact that afurther metal layer is deposited over the entire surface of theuncovered metal interconnects, and this further metal layer is then atleast partially converted into a nonconducting metal oxide, i.e., intoan insulator.

It is in this way possible to achieve significantly improved bonding ofthe dielectric layer to the metal interconnect, in particular to the Culayer, and an improved electromigration and stress migration.

In a first configuration of the invention, the metal interconnects havebeen embedded in an insulator on a substrate and have been provided witha diffusion barrier at the side walls. The further metal layer wasapplied to the uncovered metal interconnect, which may consist ofcopper, after the chemical mechanical polishing (CMP).

In a second configuration of the invention, the metal interconnects havea subtractive architecture, by virtue of the fact that a metal layer,which has been deposited over the entire surface of an insulator on thesubstrate, has been subsequently patterned, for example by RIE (reactiveion etching) or a lift-off process or the like, and the further metallayer has been deposited thereon. The metal interconnects in this caseconsist of, for example, aluminum.

A third configuration of the invention is characterized in that thefurther metal layer is applied to metal interconnects that have beenproduced by “pattern plating” (i.e., electrolytic deposition of metalinto a resist mask and subsequent removal of the resist mask) on aninsulator on the substrate.

It is expedient for the further metal layer to be converted into anonconducting metal oxide by anodic, thermal or plasma-chemicaloxidation in a back-end-compatible temperature range between 20-500° C.

In one particular configuration of the invention, the further metallayer is produced by a PVD process.

It is preferable to deposit tantalum or tantalum nitride.

According to a further configuration of the invention, a layer sequenceof Ta(N)/Ta or Ta/Ta(N) is deposited. Further materials and materialcombinations, such as Ti, Al, Ti/Al, Zr, Hf, Nb, Ru, Rh, Ir, arepossible.

Finally, it is provided that during the subsequent oxidation anonconducting metal oxide layer is produced, for example from tantalumpentoxide (Ta₂O₅) when using Ta(N), the aim being to achieve a higherdensity and quality of the layer, good bonding and a clear, definedinterface.

In a variant of the invention, it is possible to remove regions of thefurther metal layer during the subsequent oxidation, so that at thislocation a resistor made from Ta(N) is formed and is contact-connectedvia the metal layer (e.g., Cu) below.

It is preferable for parts of the further metal layer to be covered withan SiO₂ or Si₃N₄ layer.

Finally, in a further configuration of the invention, it is providedthat the tantalum pentoxide is formed partly as a MIM dielectric forintegration of a MIM capacitor.

The Ta(N) resistor and the MIM capacitor can be integrated individuallyor simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is to be explained in more detail below on the basis of anexemplary embodiment using Ta(N). In the associated drawings:

FIG. 1 shows a Cu level located on a substrate following the CMP, and aPVD-Ta(N) layer deposited thereon as further metal layer;

FIG. 2 shows the substrate from FIG. 1 following the deposition of adelimited SiO₂ layer on the Ta(N) layer;

FIG. 3 shows the substrate following the oxidation of the free Ta(N)layer to form tantalum pentoxide, with the layer of the Ta(N) layer thathas been covered with SiO₂ remaining unchanged and subsequently forminga Ta(N) resistor;

FIG. 4 shows the substrate following the deposition of a further metallayer and patterning of the latter to form the upper electrode of a MIMcapacitor together with a Ta(N) resistor, which has previously beenproduced;

FIG. 5 shows the substrate following the deposition of a further SiO₂layer, which serves as an intermetal dielectric; and

FIG. 6 shows the substrate after processing of a further interconnectlevel and of through-contacts between the two levels.

The following list of reference symbols can be used in conjunction withthe figures:

-   1 Substrate-   6 SiN layer-   2 SiO₂-   7 Metal oxide-   3 Cu metallization/metal interconnect-   8 Ta(N) resistor-   4 Through-contacts-   9 MIM capacitor-   5 Further metal layer

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 shows a substrate 1, for example made from silicon, with a Cumetallization 3, which has been embedded in an SiO₂ layer 2 (Damascene)and has been electrically connected to a lower-lying Cu level viathrough-contacts 4 made from Cu or another metal, such as tungsten. Theuncovered Cu metallization 3, following a CMP (chemical mechanicalpolishing) process, has been covered with a further metal layer 5, e.g.,a Ta(N) layer, by a PVD process. The bonding of a PVD-Ta(N) metal layeris generally better than when using layer systems that have beenproduced using CVD processes, since, for example, undesirable chemicalprocesses at the interfaces are eliminated in the PVD process and thekinetic energy of the sputtered particles is higher when they firststrike the surface on which they are to be deposited.

The boundary layer, which is in this case produced, corresponds to thesurrounding barrier and means that a comparable resistance toelectromigration can be expected. Beneath the Cu metallization 3 thereis also an optional SiN layer 6 as a diffusion barrier and etching stoplayer.

The deposition of, for example, PVD Ta, PVD Ta(N), PVD Ta(N)/Ta, PVDTa/Ta(N) or other materials and material combinations, such as Ti, Al,Ti/Al, Zr, Hf, Nb, Ru, Rh, Ir, is suitable for the further metal layer5. However, since this further metal layer 5, as a metallic coveringlayer, would short-circuit all the interconnects in this level, thislayer is completely converted into a nonconducting layer of a metaloxide 7, such as for example tantalum pentoxide. This can easily beachieved for example by thermal oxidation, which can take place in aback-end-compatible temperature range between 20 and 500° C.

The above-mentioned materials are in this case converted into acorresponding metal oxide, i.e., a dielectric, such as for exampleTa₂O₅, Al₂O₃, HfO₂, Nb₂O₅, RuO₂, Rh₂O₃, Ir₂O₃, etc. (FIG. 2).

However, if for example a Ta(N) resistor 8 (TFR resistor) is to beproduced between two through-contacts 4, the corresponding region of thefurther metal layer 5 is covered with SiO₂ prior to the oxidation (FIG.3).

Another option is to use and integrate anodically/thermally oxidizedTa/N for MIM capacitors 9 (MIM=metal, insulator, metal). To achievethis, the Ta(N), which has been deposited over a large area, is notprotected in the region where the MIM capacitor is to be formed, so thatthis region is oxidized to form Ta₂O₅ and serves as dielectric for theMIM capacitor (FIGS. 4, 5).

FIG. 6 shows a Cu level that has been passivated with tantalum pentoxideand includes a Ta(N) resistor 8 and a MIM capacitor 9 with Ta₂O₅ asdielectric.

The invention makes it possible to produce a significantly improvedbarrier interface for metallic interconnect systems by means of ametallic coating, which is substantially completely oxidized in thefollowing process, so as to form a nonconducting metal oxide.

The underlying idea of the invention is in converting an applied metallayer (further metal layer 5) into a dielectric (metal oxide 7) andusing the dielectric layer produced in this way for various applications(passivation, stop layer, MIM dielectric, etc.).

Al₂O₃, HfO₂, Nb₂O₅, etc. can also be used as MIM dielectric.

1. A process for producing a multifunctional dielectric layer on asubstrate, the process comprising: forming a plurality of metalinterconnects that are embedded in an insulator and have been providedwith a diffusion barrier at the side walls; applying a further metallayer to uncovered portions of the metal interconnects as a metalliccovering, the further metal layer comprising a metal, a metal nitride ora layer sequence of these materials; and converting the further metallayer into a nonconducting metal oxide thereby forming a dielectriclayer.
 2. The process as claimed in claim 1, wherein the dielectriclayer comprises a barrier layer on at least some interconnects.
 3. Theprocess as claimed in claim 1, wherein the dielectric layer comprises acapacitor dielectric for at least one of the interconnects.
 4. Theprocess as claimed in claim 1, further comprising covering parts of thefurther metal layer such that the covered parts form resistors.
 5. Theprocess as claimed in claim 1, wherein the metal interconnects comprisea material selected from the group consisting of copper, aluminum,tungsten, and gold.
 6. The process as claimed in claim 1, wherein thefurther metal layer is deposited on the metal interconnects, which havea subtractive architecture, by virtue of a metal layer that has beendeposited over the entire surface of an insulator on the substratehaving subsequently been patterned.
 7. The process as claimed in claim6, wherein the metal interconnects comprise aluminum, copper, tungsten,silicides, or nitrides.
 8. The process as claimed in claim 1, whereinthe further metal layer is applied to metal interconnects that have beenproduced by pattern plating on an insulator on the substrate.
 9. Theprocess as claimed in claim 1, wherein converting the further metallayer into a nonconducting metal oxide is carried out by a thermaland/or anodic and/or plasma-chemical oxidation.
 10. The process asclaimed in claim 1, wherein the oxidation takes place in a temperaturerange between 20-500° C.
 11. The process as claimed in claim 1, whereinthe further metal layer is formed by a PVD process.
 12. The process asclaimed in claim 1, wherein the diffusion barrier is formed bydepositing tantalum.
 13. The process as claimed in claim 1, wherein thediffusion barrier is formed by depositing Ta(N).
 14. The process asclaimed in claim 1, wherein the diffusion barrier comprises Ti, Al, Zr,Hf. Nb, Ru, Rh, and/or Ir.
 15. The process as claimed in claim 1,wherein regions of the further metal layer are removed during theconverting.
 16. The process as claimed in claim 1, wherein parts of thefurther metal layer are covered with an SiO₂ or Si₃N₄ layer during theconverting.
 17. The process as claimed in claim 1, wherein a metal thinfilm resistor and a MIM capacitor are at least partially formed by thesteps of forming a further metal layer and converting the further metallayer.
 18. A process for producing a multifunctional dielectric layer onan uncovered metallic interconnect system on a substrate, theinterconnect system including metal interconnects that have beenembedded in an insulator on a substrate and have been provided with adiffusion barrier at side walls, the method comprising: performing achemical mechanical polishing process to expose an upper surface of themetal interconnects; applying a further metal layer, formed from ametal, a metal nitride or a layer sequence of these materials, to theuncovered metal interconnects as a metallic covering layer following thechemical mechanical polishing process; and converting portions of thefurther metal layer into a nonconducting metal oxide thereby forming adielectric layer as a barrier layer on some interconnects and as acapacitor dielectric on other interconnects, wherein portions of thefurther metal layer, which have been covered, are not converted and formresistors.